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November 2006 rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer
PCS2P5T9050A
Features
* * * * * * * * * * Optimized for 2.5V LVTTL Guaranteed Low Skew < 25pS (max) Very low duty cycle distortion< 300pS (max) High speed propagation delay < 1.8nS. (max) Up to 200MHz operation Very low CMOS power levels Hot Insert able and over-voltage tolerant inputs 1:5 fan-out buffer 2.5V Supply Voltage Available in TSSOP Package
The PCS2P5T9050A 2.5V single data rate (SDR) clock buffer is a single-ended input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fan-out from a single input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise.
Applications:
PCS2P5T9050A is targeted towards Clock and signal distribution applications.
Functional Description Block Diagram
GL
G
OUTPUT CONTROL
Q1
OUTPUT CONTROL A OUTPUT CONTROL
Q2
Q3
OUTPUT CONTROL
Q4
OUTPUT CONTROL
Q5
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006 rev 0.2
Pin Configuration- Top View - TSSOP Package
PCS2P5T9050A
GL VDD GND G VDD Q1 GND A Q5 VDD GND VDD VDD NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
GND VDD GND GND VDD Q2 GND Q3 Q4 VDD GND GND VDD NC
PCS2P5T9050A
22 21 20 19 18 17 16 15
Pin Description
Symbol
A G
I/O
I I
Type
LVTTL LVTTL Clock input
Description
Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously disabled to the level designated by GL1. Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW. Clock outputs Power supply for the device core, inputs, and outputs Power supply return for power
GL Qn VDD GND
I O
LVTTL LVTTL PWR PWR
NOTE: 1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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Absolute Maximum Ratings Symbol
VDD VI VO TSTG TJ
PCS2P5T9050A
Description
Power Supply Voltage Input Voltage Output Voltage Storage Temperature Junction Temperature
Max
-0.5 to +3.6 -0.5 to +3.6 -0.5 to VDD +0.5 -65 to +165 150
Unit
V V V C C
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Capacitance1 (TA = +25C, F = 1.0MHz) Symbol
CIN
Parameter
Input Capacitance
Min
Typ
6
Max
Unit
pF
NOTE: 1. This parameter is measured at characterization but not tested.
Recommended Operating Range Symbol
TA VDD
Description
Ambient Operating Temperature Internal Power Supply Voltage
Min
-40 2.3
Typ
+25 2.5
Max
+85 2.7
Unit
C V
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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DC Electrical Characteristics Over Operating Range1 Symbol
IIH IIL VIK VIN VIH VIL VOH
PCS2P5T9050A
Parameter
Input HIGH Current Input LOW Current Clamp Diode Voltage DC Input Voltage DC Input HIGH2 DC Input LOW3 Output HIGH Voltage
Test Conditions
VDD= 2.7V VDD= 2.7V VI = VDD/GND VI = GND/VDD
Min
Typ4
Max
5 5
Unit
A
VDD= 2.3V, IIN= -18mA -0.3 1.7
-0.7
- 1.2 +3.6
V V V
0.7 IOH= -12mA IOH= -100A VDD- 0.4 VDD- 0.1 0.4 0.1
V V V V V
VOL
Output LOW Voltage
IOL= 12mA IOL= 100A
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Voltage required to maintain a logic HIGH. 3. Voltage required to maintain a logic LOW. 4. Typical values are at VDD = 2.5V, +25C ambient.
Power Supply Characteristics Symbol
IDDQ Current Dynamic VDD Power Supply Current per Output
Parameter
Quiescent VDD Power Supply
Test Conditions1
VDD= Max., Reference Clock = LOW Outputs enabled, All outputs unloaded VDD= Max., CL= 0pF VDD= 2.5V., FREFERENCE CLOCK = 100MHz,
Typ
1
Max
1.5
Unit
mA
IDDD
100
150
A/MHz
ITOT
Total Power VDD Supply Current
CL= 15pF VDD= 2.5V., FREFERENCE CLOCK = 200MHz, CL= 15pF
50
65 mA
75
100
NOTE: 1. The termination resistors are excluded from these measurements.
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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Input AC Test Conditions Symbol
VIH VIL VTH tR, tF Input HIGH Voltage Input LOW Voltage Input Timing Measurement Reference Level1 Input Signal Edge Rate2
PCS2P5T9050A
Parameter
Value
VDD 0 VDD/2 2
Units
V V V V/nS
NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
AC Electrical Characteristics Over Operating Range4 Symbol Skew Parameters
tSK(O) tSK(P) tSK(PP)
Parameter
Min
Typ
Max
25 300 300
Unit
pS pS pS
Same Device Output Pin-to-Pin Skew1 Pulse Skew2 Part-to-Part Skew3
Propagation Delay
tPLH tPHL tR tF fO Propagation Delay A to Qn Output Rise Time (20% to 80%) Output Fall Time (20% to 80%) Frequency Range 350 350 1.8 850 850 200 nS pS pS MHz
Output Gate Enable/Disable Delay
tPGE tPGD Output Gate Enable to Qn Output Gate Enable to Qn Driven to GL Designated Level 3.5 3 nS nS
NOTES: 1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device. 2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device. 3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels and temperature. 4. Guaranteed by design.
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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AC Timing Waveforms
PCS2P5T9050A
Propagation and Skew Waveforms
NOTE: Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse.
Gate Disable/Enable Showing Runt Pulse Generation
NOTE: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their G signal to avoid this problem.
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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November 2006 rev 0.2
Test Circuit and Conditions
PCS2P5T9050A
Test Circuit for Input/Output Input/Output Test Conditions Symbol
VTH R1 R2 CL
VDD= 2.5V 0.2V
VDD/ 2 100 100 15
Unit
V pF
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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Package Diagram 28L TSSOP (173 mil)
PCS2P5T9050A
Dimensions Symbol
A A1 A2 D L E E1 R R1 b b1 c c1 L1 e
Inches Min Max
.... 0.0020 0.031 0.3779 0.020 0.169 0.004 0.004 0.007 0.007 0.004 0.004 0.043 0.0059 0.041 0.3858 0.030 0.177 .... .... 0.012 0.010 0.008 0.006
Millimeters Min Max
... 0.05 0.80 9.60 0.50 4.30 0.09 0.09 0.19 0.19 0.09 0.09 1.2 0.15 1.05 9.80 0.75 4.50 ..... ..... 0.30 0.25 0.20 0.16
0.252 BSC
6.40 BSC
0.039 REF 0.026 BSC 0 12 REF 12 REF 8 0
1.0 REF 0.65 BSC 8 12 REF 12 REF
1 2 3
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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Ordering Information Part Number
PCS2P5T9050AF-28TT PCS2P5T9050AF-28TR PCS2I5T9050AF-28TT PCS2I5T9050AF-28TR PCS2P5T9050AG-28TT PCS2P5T9050AG-28TR PCS2I5T9050AG-28TT PCS2I5T9050AG-28TR
PCS2P5T9050A
Marking
2P5T9050AF 2P5T9050AF 2I5T9050AF 2I5T9050AF 2P5T9050AG 2P5T9050AG 2I5T9050AG 2I5T9050AG
Package Type
28 Pin TSSOP, Tube, Pb Free 28 Pin TSSOP, Tape and Reel, Pb Free 28 Pin TSSOP, TUBE, Pb Free 28 Pin TSSOP, Tape and Reel, Pb Free 28 Pin TSSOP, Tube, Green 28 Pin TSSOP, Tape and Reel, Green 28 Pin TSSOP, TUBE, Green 28 Pin TSSOP, Tape and Reel, Green
Operating Range
Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial
Ordering Information
PCS2P5T9050AF-28TR
OR - TSOT23 -6,T/R TT - TSSOP, TUBE TR - TSSOP, T/R VT - TVSOP, TUBE VR - TVSOP, T/R ST - SOIC, TUBE AR - SSOP, T/R AT - SSOP, TUBE PIN COUNT LEAD FREE PART F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS X = Automotive (-40C to +125C) I = Industrial P or n/c = Commercial (-40C to +85C) (0C to +70C) 6 - power management 7 - power management 8 - power management 9 - Hi performance 0 - reserved SR QR QT BT BR UR DR DT - SOIC, T/R - QFN, T/R - QFN, TRAY - BGA, TRAY - BGA, T/R - SOT-23, T/R - QSOP, T/R - QSOP, TUBE
1 - reserved 2 - Non PLL based 3 - EMI Reduction 4 - DDR support products 5 - STD Zero Delay Buffer
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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November 2006 rev 0.2
PCS2P5T9050A
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P5T9050 Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use..
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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